How does the system know that the downstream block is on host or FPGA?

On Fri, Dec 5, 2014 at 8:58 AM, Nowlan, Sean
<sean.now...@gtri.gatech.edu> wrote:
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>>Ettus Research is very excited to announce the release of RFNoC!
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> […]
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> This is very cool. I’ve been looking forward to working with this
> development.
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>> Mixing and matching host-based and FPGA-based processing is transparent to
>> the user, and that processing can scale across multiple FPGAs and devices
>> across a network
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> Does this imply that I could run a GNU Radio application on a Zedboard, for
> instance, with the following data flows:
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> (1) GR on Zynq ARM --> Zynq FPGA --> GR on Zynq ARM --> B2x0 RF/radio
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> (2) GR on Zynq ARM --> Zynq FPGA --> GR on Zynq ARM --> X3x0 FPGA --> X3x0
> RF/radio
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> I think (1) is similar or identical to Jonathon Pendlum’s FPGA filter demo.
> What I’m more curious about is how easy it is to build a single GR flowgraph
> that mixes GR processing with FPGAs that live either in Zynq or connected
> 3x0 series devices. It sounds like this kind of support is an explicit goal
> of RFNoC.
>
>
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