> Regardless of whether you use the stock FPGA design or a custom one to do raw > data capture you are going to run up against the basic limits of 1GB/s > i.e 1Gb/S = 125MB/S = 62.5M 16bit samples/S > > The stock image is always going to want to send an I and Q channel, and has > the option of either 25MSamples/S @ 16bit or 50MSample/S @ 8bits and it's > going to pass the data through either 1 or 2 low pass FIR filters to decimate > to that data rate. > Even if you write a very custom FPGA design that packs 14bit data efficiently > and uses a raw UDP transport, you would be doing well to achieve 70MSample > @14bits over ethernet since real world performance never quite matches > theoretical.
Thanks for your reply, I think I'll go ahead and order one to play with. I can live with 25MSamples/S for the moment and try and do some compression later. The I/Q stuff is more worrying, I guess I can always convert back to real in software on the host? It would be nicer not to have to so I may try looking at the Verilog and see how easy it would be to make these changes. Alternatively if there's a contractor out their who would be interested in doing this please mail me! _______________________________________________ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org https://lists.gnu.org/mailman/listinfo/discuss-gnuradio
