Hi Guys,

I am using N210 with SBX at 5M sampling rate. I have one USRP Source
running continuously (connected to the TX/RX antenna), and a USRP Sink
(connected also to TX/RX) that sends timed packets with the tx_time,
tx_sob, tx_eob tags at a rate of 1 ms per packet. I am sending packets
10 ms prior to the USRP Sink and I use the sample counter of the USRP
Source to monitor the time on the FPGA.

After some time I am observing timing errors (L) that I cannot
explain. The only possible explanation would be a sampling glitch in
the RX path when switching between TX and RX. That is, it seems that a
few samples are lost in the RX path when the switch is made, and
therefore the FPGA time and the number of samples received are
diverging over time (by a small amount for each switch). I do not
observe this behavior at 500K sampling rate, there no RX samples seem
to be lost. There are no underruns/overruns prior to the lots of L's.

Any ideas why this is happening and whether it can be prevented somehow?

Miklos

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