Hi josh,
thank's for the hint - but this is not quite what I want to do:
In the future I want to use 4 separate inputs - this is for a
network-analyzer with 2 directional couplers for S11, S21, S12, S22.
For a start I want to use only RX-board A with 2 different signals on
both inputs. This implies that the Q-inputs of the DDCs must be
connected to 0.
I guess the subdev spec would be:
"A:A A:B" ?
What would be the setting to use all 4 input?
Thanks
Wolfgang
On 05/26/2013 05:00 AM, Wolfgang Buesser wrote:
> Hello,
>
> I using a usrp1 populated with 2 LF-RX and 2 LF-TX.
> I want to use 2 DDCs the I-inputs of which are connected to the 2 ADCs on
> LF_RX A (Q-inputs to gnd).
>
> In pre-uhd times I used to use set_mux, but now the API seems to have changed.
> The following code produces the error message:
>
> AttributeError: 'uhd_usrp_source_sptr' object has no attribute 'set_mux'
>
> How can I control the mux in the RX-path of the usrp1?
>
Set the subdevice specification to "A:A B:A". This maps the DDC0 to
dboard A, frontend A and DDC1 to dboard B, and frontend A.
-josh
> Wolfgang
>
>
> #!/usr/bin/python
>
>
>
>
> from gnuradio import gr
> from gnuradio import uhd
> from gnuradio.eng_option import eng_option
>
>
> class build_block(gr.top_block):
> def __init__(self):
> gr.top_block.__init__(self)
>
> self.u_tx = uhd.usrp_sink("serial=47432785",uhd.stream_args('fc32'))
> self.u_tx.set_samp_rate(8.0e6)
> self.siggen_tx =
> gr.sig_source_c(self.u_tx.get_samp_rate(),gr.GR_CONST_WAVE,0, 1.0, 0)
> # self.head_tx = gr.head(gr.sizeof_gr_complex, 1000000)
>
>
>
> self.head_tx = gr.head(gr.sizeof_gr_complex, 1000)
> self.u_tx.set_subdev_spec("A:AB",0)
> self.u_tx.set_center_freq(10e6)
>
> self.u_rx = uhd.usrp_source("serial=47432785",uhd.stream_args('fc32'))
> self.u_rx.set_mux(gru.hexint(0xf0f0f1f0))
> self.u_rx.set_center_freq(10e6+1e3)
> self.head_rx_0 = gr.head(gr.sizeof_gr_complex, 1000)
> self.dst0 = gr.file_sink(gr.sizeof_gr_complex, "r.dat")
>
> # self.di = gr.deinterleave(gr.sizeof_gr_complex)
>
>
>
>
> self.connect (self.siggen_tx,self.head_tx, self.u_tx)
> self.connect (self.u_rx,self.head_rx_0,self.dst0)
>
> tb = build_block ()
> tb.run ()
>
>
>
>
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>
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--
Wolfgang Buesser
Am Ziegelberg 1a
55595 Mandel
+49 174/585 2995
wolfgang.bues...@web.de
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