Thanks Josh,
What I am looking for on the TX side of things is basically the same thing
I have on the RX side. If I set the subdev spec on the basic RX to "A:A
A:B" and then use usrp->set_rx_freq(uhd::tune_request_t(freq)) for each
channel, I get two separate rx channels, both with their own IQ pairs. On
the TX side I only manage to have one IQ pair, as in I through TX_A and Q
through TX_B. We were trying for a 4 channel transmit on 2 USRPs, so that
they could all be connected by s MIMO cable. One more question, when you
say "too complicated to be worth it", generally, what kind of modification
would be necessary?
Thanks for your time!
-Anisha

On Fri, Sep 28, 2012 at 6:36 PM, Josh Blum <j...@ettus.com> wrote:

>
>
> On 09/28/2012 08:49 AM, Anisha Gorur wrote:
> > Hello All,
> >
> > I am using a USRP N210. When i set the subdev spec for my basic RX
> > daughterboard as "A:A A:B" I can receive two channels. However, if I try
> to
> > do something similar for the basic TX I get an error like "The user
> > specified 2 channels, but there are only 1 tx dsps on mboard 0." I assume
> > this is because there is only one DUC chain in the N210. Is there a way
> to
> > modify this so that I can have two DUC chains in the same way that I have
> > two DDC chains?
> > Thanks,
> > Anisha
>
> I think adding two complete DUC chains into N210 would be too
> complicated to be worth it.
>
> Is there something specific that you cant do with the single DUC chain?
> As long as the cordic is set to zero, I and Q will remain completely
> separate from host samples, all the way to the SMA connectors A and B.
>
> Otherwise, perhaps you need a different rotation for I vs Q? I think
> that would be better accomplished by two different cordics. Then perhaps
> a custom DSP in the FPGA is for you:
>
> http://code.ettus.com/redmine/ettus/projects/uhd/repository/revisions/master/entry/fpga/README.txt#L29
>
> I hope that helps.
>
> -josh
>
> >
> >
> >
> > _______________________________________________
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> >
>
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-- 
Anisha Gorur
Class of 2012
Electrical Engineering
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