hi, i am also trying to modify the verilog code in usrp fpga. mail me if you have hello world program to do that. I am not understanding how to do it exactly. thanks in advance.
Balijepalli, Arvind wrote: > > I am starting to look into building a feedback controller, which takes the > position of the particle and outputs a suitable control signal. The > controller itself will most likely be a tabulated function, which we can > implement using a lookup table. However, I am having trouble getting a > basic signal echo going. I have installed GNU radio as well as the Quartus > compiler and worked through compiling and running the top level std_usrp > project. > > As a next step, I am trying to modify the USRP FPGA Verilog code to build > a simple signal echo. The Verilog code is extremely simple in this case. I > started by modifying to top level usrp_std.v and simply mapped the input > rx_a_a and rx_b_a onto tx_a and tx_b, cutting out all the other extraneous > code pertaining to the USB. The essence of the Verilog code is: Create two > registers to drive the output wires and echo the output at the positive > edge of the clock. This code compiles without errors in Quartus (although > this doesn't necessarily imply that it should work). > > reg lTXA; > reg lTXB; > > assign tx_a = lTXA; > assign tx_b = lTXB; > > always @(posedge clk64) > begin > lTXA = rx_a_a; > lTXB = rx_b_a; > end > > > However, I am not sure how to setup the python code to get this to > successfully run. The code snippet below doesn't seem to do the trick. > > > src = usrp.source_c(which=0, decim_rate=64, nchan=2, mode=0, > fpga_filename="echo.rbf") > dst = usrp.sink_c(which=0, nchan=2) > > self.connect (src, dst) > > Can someone point me in the right direction with this? Also, I haven't > found a simple "hello, world!" example to modify the FPGA code. Does such > an example exist? If it doesn't, I will be happy to get this to a point > where it is usable and submit it back to the community. I think it may be > useful for others like myself who are new to Verilog/FPGAs and may provide > an easier entry point to start modifying the FPGA code. > > > Thanks, > Arvind > -- > Arvind Balijepalli > > NIST > 100 Bureau Drive, Mail Stop 8212 > Gaithersburg, MD 20899 > > > _______________________________________________ > Discuss-gnuradio mailing list > Discuss-gnuradio@gnu.org > http://lists.gnu.org/mailman/listinfo/discuss-gnuradio > > -- View this message in context: http://old.nabble.com/Simple-signal-echo-with-the-USRP-tp28348387p33765406.html Sent from the GnuRadio mailing list archive at Nabble.com. _______________________________________________ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org https://lists.gnu.org/mailman/listinfo/discuss-gnuradio
