Hi! I'm planing on adding CUSTOM_DEFS to the USRP2 FPGA image, that I want to extend with custom Verilog modules. (http://code.ettus.com/redmine/ettus/projects/uhd/repository/revisions/master/entry/fpga/README.txt)
I want to do this in a minimal invasive way, using some of the Simulink Xilinx development stuff, that there is. Especially I want to keep the DDC/DUC routines as they are for now, which are part of the DSP. As far as I understand it a custom definition will completely substitute any of the chain engines. Is there a way to be less destructive about that? Also I'm looking for what the current chains exactly are: is there some sort of flow-graph here. Did somebody already analyse this? There are some custom FPGA builds here and there. I'd be happy if someone contributed insights how to touch this without having to redo everything. Best, Marius
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