Dear sir. Could anybody give me the direction that how to do or known the
reason? In the USRP board of N210, in order to get 7.68M sampling rate with
non-resample, I use Crystek 76.8Mhz instead of 100MHz, but the problem is that
couldn't demodulate the signal. I change the files as following: 1.
/host/lib/usrp/usrp2/clock_ctrl.cpp double get_master_clock_rate(void){
return 76.8e6; } //Original is 100e6 2. /firmware/zpu/lib/memory_map.h
#define MASTER_CLK_RATE 76800000 // Original is 100000000 3.
/firmware/zpu/bin/divisors.py master_clk = 76.8e6 //Original is 100e6
4. /fpga/usrp2/models/adc_model.v real freq = 330000/76800000;
//Original is 330000/100000000 5. /host/lib/usrp/usrp2/usrp2_impl.cpp
(ups_per_sec > 0.0)? size_t(76.8e6/*Original is 100e6, approx tick
rate*//ups_per_sec) : 0, Then I run "make" in host, firmware and fpga also,
bin files written to FPGA already, but it still can not demodulate correctly.
Could you please tell me where is possible to change also? or what's the
problem? thanks a lot. _______________________________________________
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