Hi, Anyone here implemented freq/phase correction and symbol timing correction in USRP's FPGA?
Recently I implemented Costas loop and Muller & Mueller algorithm in RTL by referring the gnuradio code. Now I'm testing it on FPGA. I can get correct demodulated data(DQPSK) at initial few thousand symbols. After that I'm getting all rubbish data. I think the problem with my RTL implementation is not good enough bit-resolution (unlike implementation on PC). Currently I'm using 15-bits resolution for decimal part. Anyone has any suggestion ? PN
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