On 09/27/2011 06:04 PM, Philip Balister wrote:
I see a couple of possibilities;
1) Use a microblaze in the fpga to control the spi bus and other
control functions. (It may already use a microblaze, so update the
code to do this internally, instead of taking commands from ethernet)
There's a ZPU in the FPGA--it handles some of the protocol and low-speed
interfacing "goop" in the normal firmware/FPGA load.
But the general "model" is that the FPGA/firmware is "dumb". It
simply provides a fairly generic "peek and poke" interface over
the Ethernet, with all the "smarts" in the host code. I think part
of the motivation for this is that it's easier to modify host code
for minor performance tweaks, etc, than doing it in the firmware/FPGA
code. But one could certainly enhance the small amount
of firmware that runs on the ZPU to handle all the device register
initialization, etc.
--
Marcus Leech
Principal Investigator
Shirleys Bay Radio Astronomy Consortium
http://www.sbrac.org
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