>>> But from my tests I see that
>>> 1 bit error in -> 7 bit errors out
>>> 2 consecutive bit errors in -> 2 errors in the output
>>> 3 consecutive bit errors in -> 7 errors in the output
>>> 4 consecutive bit errors in -> 4 errors in the output
>>> ...
>>> And so forth up to 7 (Length of the lfsr)
>>>
>>> The reason I ask is that if I want to change the scrambler and/or the
>>> modulation, I assume that this "magic number" will change as well.
>>
>> If you want a good BER measurement, I wouldn't use the method that you
>> describe here.
>
>You are correct.  The scrambler introduces three output errors per
>input error for single channel errors that are farther apart than the
>length of the shift register.  This is the case once the shift
>register has already achieved self-synchronization and at low channel
>error rates.  For the purposes of the simple BERT example, this was
>sufficient.  (The number 3 comes from the number of taps in the
>scrambler polynomial.)

I know this thread is a bit old, but is it possible that there is an mistake in 
the text?

I think it should be written, that 1 bit error in the scramber input introduces 
4 errors in the output, because 1 error is passed directly through and 3 
feedback errors are introduced by the taps in the scrambler polynomial of:

self._descrambler = gr.descrambler_bb(0x8A, 0x7F, 7) # CCSDS 7-bit descrambler

If I'm wrong, don't hesitate to correct me. Thanks.

Daniel

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