This is quick and off the top of the top of my head but here are some clues:
1)The appropriate Makefile.srcs should call both 'fifo_xlnx_2Kx36_2clk.v' and ''fifo_xlnx_2Kx36_2clk.xco' 2) In the log (capture all ISE output to a file for review by redirecting STDOUT) you should see the following lines if you grep for fifo_xlnx_2Kx36_2clk: >>> Adding source to project: >>> /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v >>> Adding source to project: >>> /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco Compiling verilog file "../../../coregen/fifo_xlnx_2Kx36_2clk.v" in library work Module <fifo_xlnx_2Kx36_2clk> compiled Reading core <../../../coregen/fifo_xlnx_2Kx36_2clk.ngc>. 3) Coregen should automatically build this block from the spec in the .xco file to create the .ngc data read my ISE. You could try running coregen in the 'coregen' subdirectory to see if it can build it manually. Sometimes there can be issues with different versions of the FIFO generator tool included in ISE vs that specified in the .xco file. Report back with grep output from your log if you can't crack this. -Ian On Feb 16, 2011, at 9:33 AM, Gabriel Morel wrote: > Hi, I finally managed to run ISE 10.1 on Linux to compile the raw internet > version of the fpga project, > but when I call 'make bin', the following error appears: > > ERROR:HDLCompilers:87 - "../../../fifo/fifo_2clock.v" line 26 Could not find > module/primitive 'fifo_xlnx_2Kx36_2clk' > > I checked in the makefile to be sure all is called well and the file above is > in there. Anybody know why? > > Am I obligated to update to sp3? > > Thx > Gabriel > _______________________________________________ > Discuss-gnuradio mailing list > Discuss-gnuradio@gnu.org > http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
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