I've posted my latest thoughts at:
http://www.sbrac.org/files/digital_receiver2.pdf
This version has some BOM cost estimates for most of the items, and
shows a new
PLL, the ADF4351, which is a new chip from AD, coming out later this
spring, which
is pin compatible with the ADF4350, and includes a lower minimum
output frequency, which
means extending the range downwards to about 18MHz from about 68MHz.
Cool.
Going to a AD6652 (which has built-in DDC and CIC decimators) increases
the price of the
ADC by a factor of 3, but it would eliminate the need for a FPGA on
the "host interface"
side of that FMC connector. So, you're trading a more expensive
digital-receiver section
for a cheaper "host interface" section. For example, by using an
AD6652, one could
easily conceive of nothing more than a cheap EZ-FX2 USB-2.0
implementation on
the host-interface side.
For at least USB-3.0 and 1GiGe, you pretty-much *need* an FPGA on the
host-interface board
to do all the relevant protocol goop anyway, so perhaps making that
FPGA large enough
to do DDC and CIC decimation as well as the "host interface goop" is
the right trade-off.
Love to hear more opinions
--
Marcus Leech
Principal Investigator
Shirleys Bay Radio Astronomy Consortium
http://www.sbrac.org
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