Matt Ettus wrote:
>
>
> This is due to truncation in the USRP. If you add 0.5 to the signal, it
> should go away.
>
> Matt
>
>
>
Dear Matt,
how and where does the truncation is done? is it in the FPGA (DDC) ?
regards,
Adib
-----
Mohd Adib Sarijari
Universiti Teknologi Malaysia
www.fke.utm.my
www.utm.my
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