On Sat, Oct 9, 2010 at 11:25, Matt Ettus <m...@ettus.com> wrote:
> On 10/08/2010 07:10 PM, Mark J. Blair wrote:
>>
>> On Sep 25, 2010, at 10:41 AM, dburg...@kestrelsp.com wrote:
>>>
>>> We would have used 13 MHz, but the USRP-1 FPGA code fails to transmit for
>>> clock rates below about 48 MHz.
>>
>> Does anybody know why this is?
>>
>
> That is not correct.  The inband signaling code that OpenBTS uses may not
> work with those clock rates, but the standard code we developed works just
> fine with any clock frequency.  I have used it all the way down to 10 MHz.

I believe that it's still doesn't work as expected at low clock rates.
While FPGA code may support this, ADC or DAC (don't recall exactly)
need a different configuration of capacitors/resistors - USRP use
default configuration from the datasheet, which is suitable for high
clock rates. That's from my memories, so I may be wrong somewhere.


-- 
Regards,
Alexander Chemeris.
http://www.fairwaves.ru

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