On 09/02/2010 05:11 PM, Malihe Ahmadi wrote: > Hi MArcus, > Assuming I want to use Ethernet, let's say I want to send the stream > '0100001', and I pick DBPSK as the modulation. can you please explain > what is the relation of the DBPSK modulated data and "GMII_RXD" input > to the FPGA or "sample" input to the dsp_core_tx? is that FPGA > receives 8 bits per symbol sent over Ethernet? > Also, can I get those occasional programming instructions you > mentioned to be hard-coded (for example changing the firmware so that > it uses some default values instead of passing those values through > GiGe) if I am interested in removing Ethernet and using debug bus to > pass stream of data to the FPGA? > Thanks, > Malihe > Marcus D. Leech wrote: Well, I'm not an expert in the way the FPGA works internally, nor on the signals going into or out of if, but the GMII_RXD pin is likely the RXD pin from the 1GiG Ethernet Phy.
Your DBPSK modulated bits stream is represented as a discrete-sampled time-series, those (complex) samples are presented to the Ethernet interface, sent over the Ethernet to the FPGA, where those samples are possibly interpolated by the FPGA up to the sample rate of the A/D (200MHz), from the output side of the A/D the signal is a complex analog baseband representation of the signal, which is then typically upconverted to the final target frequency. The normal way that discrete-sampled time series gets to appear at the FPGA is that the resulting waveform is created by a Gnu Radio "flow graph" that includes the proper modulation "stuff" to take a series of bits (like your 0100001) and turn it into a complex baseband waveform. Now, you want to avoid the SDR aspects altogether, and do "everything" inside the FPGA. So you want to use the USRP2 essentially as your wireless "PHY", and totally ignore the SDR aspects of the USRP2 design. You want to know if there are pins available on the FPGA to allow it to take your bits (and related clocks), and have the FPGA do the necessary modulation and spreading, in a standalone manner. I think Eric Blossom already mentioned the MICTOR interface, which may do what you want. Assuming that the MICTOR or some other interface on the FPGA will do what you want, and there's enough room inside the FPGA, then I don't see that you'll have a problem. You can certainly hard-code whatever daughter-card setup you need inside the firmware. You'll find that if you want detailed help making this work, you'll have a hard time finding anyone who'll give you that help for free. The FPGA and aeMB firmware is freely available, and you'll likely get some hints and tips from time to time. But what you're contemplating is a fairly major project that is, to a first approximation, outside of the strict confines of Gnu Radio. -- Marcus Leech Principal Investigator Shirleys Bay Radio Astronomy Consortium http://www.sbrac.org _______________________________________________ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
