Hello, Have you tried the new Xilinx's FIFOs ?
All constraints were met after regenerating the FIFOs using Fifo Generator 6.1. I used ise12 branch and compiled the raw ethernet code. 2010/6/1 Matt Ettus <m...@ettus.com> > > > The USRP2 FPGA image can now be built with ISE 12.x. ISE 11.x probably > also works, but since 12 is a free upgrade from 11, I suggest you use 12. > Everything still works on ISE 10.1.03 as well. > > One additional change is that both the plain (Raw Ethernet) and UDP > versions (for UHD) are in the same tree now. Build the plain version with: > > make bin > > in the usrp2/top/u2_rev3 directory, and the UDP version can be built with: > > make -f Makefile.udp bin > > > This experimental branch is called ise12_exp and you can get it from our > git repository: > > http://code.ettus.com/redmine/ettus/projects/show/fpga > > It does not quite meet timing yet, but it is plenty good for experimental > work. We will be working on timing closure in the next couple of weeks. > Any feedback would be much appreciated. > > > > Huge thanks go to Ian Buckley for his help in this porting effort. > > Thanks, > Matt > > > _______________________________________________ > Discuss-gnuradio mailing list > Discuss-gnuradio@gnu.org > http://lists.gnu.org/mailman/listinfo/discuss-gnuradio >
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