Hello all,
I'm new to SDR, the USRP, and FPGA programming, and I was
wondering if someone could help me with a question on writing Verilog
test benches.
I'm getting a Spartan 3E dev board to play with, and to learn more about SDR
and Verilog FPGA programming, I thought it might make a nice long-term goal to
try and port the USRP1 firmware from the Cyclone
to a Spartan 3E (full disclosure: I'd love to try to make a full radio system
starting from this devboard, if I can ever get that part working).
I've finally got the USRP1 firmware, with the 4 RX channel, no halfband config
option, to compile using the Xilinx ISE Webpack targeted on Spartan 3E. I
changed the bustri module from an Altera megacell to a generic Verilog mux, and
rewrote the RX chain fifo, and I'd like to run a testbench to see if I can send
a signal in and get anything useful
out. I understand that the old USRP1 testbench, fullchip.v, is now deprecated,
and I couldn't find any discussion on the FAQs or forums or anywhere else
regarding any other toplevel test benches.
I made a (hilariously naive) attempt at writing my own testbench using Xilinx's
ISim, associated with usrp_std, linking 64 Mhz and 48 Mhz clocks to master_clk
and usbclk, respectively, inputting a square wave on the rx_a_a bus, and
holding usbctl lines OE and RD high. When I do all this, the usbdata bus goes
from 16'Z to 16'0, when RD and OE are
enabled, but that's about it. I would imagine that there are all sorts of other
registers that I would need to send commands to, maybe over the SDI/SDO or
io_rx lines, to get a response from the FPGA firmware, but after looking at the
FAQs I'm not quite sure where to start. I've included this testbench code
below, if anybody would care to comment on what else is needed to initialize
USRP1; or if someone could tell me where I could find a detailed discussion on
writing a testbench for usrp_std that's already online, I would be very
grateful.
Best Regards,
Bardus
Sample test bench code:
`timescale 1ns / 1ps
module test_sw1;
// Inputs
reg master_clk;
/*... etc.; I won't list the declarations and instantiations for
everything, but everything is named and
all inputs are initialized to 0.
// Instantiate the Unit Under Test (UUT)
usrp_std uut (
.MYSTERY_SIGNAL(MYSTERY_SIGNAL),
//// ...etc.
);
initial begin
// Initialize Inputs
master_clk = 0;
SCLK = 0;
// ...etc.
// Wait 100 ns for global reset to finish
#100;
// Assert OE and RD high
usbctl[1] = 1;
usbctl[2] = 1;
// Add stimulus here
end
// clock and rx_chain square wave generation
always #7.8125 master_clk = ~master_clk;
always #10.416667 usbclk = ~usbclk;
always #500 rx_a_a[7] = ~rx_a_a[7];
always #500 rx_a_a[1] = ~rx_a_a[1];
endmodule
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