Matt,
Thank you for your email.
The mac is all contained in simple_gemac, and above that in
simple_gemac_wrapper:
http://code.ettus.com/redmine/ettus/projects/fpga/repository/revisions/master/show/usrp2/simple_gemac
simple_gemac_wrapper in the fifo_2clock_cascade files.
which is instantiated in u2_core. Most of the buffering happens in
I would just start with the u2_core and simple_gemac_wrapper. If you're
not using the SERDES, that is a good place to start ripping out.
Does this imply that we can pull out the aeMB core, the 32K RAM and the
buffer pool under module u2_core ?
To carry out preliminary testing we need to be able to pass data to the
gemac and configure appropriate control registers. Could you please
suggest what existing modules we could reuse to send data to the gemac ?
3) Do you have an FPGA internal achitecture block diagram of any
type? Is there another group you're aware of doing such "major
modification" FPGA work that we might talk to?
There were some on the wiki at one time. If they're not still there
I'll post a talk I did which covers the architecture.
I have looked at the wiki (http://gnuradio.org/redmine/wiki/gnuradio),
however i was not able to find any block diagrams for the internal
architecture of the FPGA for USRP2. I still might not be look at the
right place. Could you please point me in the right direction ?
From forum discussions over the past couple of months it appears that
USRP2 does not support the 10/100 mode. Could you please help us
understand the work effort involved in getting the 10/100 mode working ?
Thanks and Regards,
Vikram.
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