Hi all,
I'm poking around the USRP2's CPLD, the XC9572, mainly just to understand exactly how the U2 boots, and so looking for the Verilog source code that goes into the CPLD. I find usrp2/fpga/boot_cpld/boot_cpld.v, but this file has a comment that it is "only for u2_rev2," and I'm using u2_rev3 like most others. usrp2/fpga/models/cpld_model.v looks promising too; any hints?
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