Nope, Nope, and Nope. I was rather shocked, things never go that well for me :)
I pulled the u2_rev3 and just resolved my way through the source tree. I was not expecting it to generate cleanly. I did regenerate two cores as part of the process, dumped a couple of the generated .v files because they refused to resolve properly, but the first time through they regenerated and went right through place and route with no errors, and no timing issues like I had with it earlier (set to the -4 speed grade). I just havent been able to generate the bitstream, and I won't have a chance to do any testing til next week, if I do get it resolved. Tracey On Mon, Feb 15, 2010 at 6:52 PM, Jeff Brower <jbro...@signalogic.com> wrote: > Tracey- > > > I was able to place and route the design on ISE 11.4 using a 'high' > effort > > and ensuring that the speed grade selected is -5 (that really made a > > difference of about 20MHz in the speed of the final design). However, > when > > it comes time to generate the bitstream, it complains about the -g > > Match_cycle:Auto and insists on changing it to -g Match_cycle:NoWait, > and > > then throws an error, with no information. > > You didn't have to change any source files or the constraints file? No > coregen errors? > > -Jeff > > -- Tracey Bernath 913-488-6284
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