We are currently working on a fix for the problems with compiling under
the ISE 11. We believe it to be a problem with ISE 11, since the design
works fine under ISE 10, but have not gotten very far. Any help anyone
can provide on this would be much appreciated.
Thanks,
Matt
On 01/18/2010 05:38 AM, Mahesh Poolakkaparambil wrote:
Hello ,
I have posted a query on the forum regarding "compiling
u...@_rev3 on ISE11.1 ", I still could not find a good remedy for this.
I am attaching the error message with this mail. i hope this will help
form some one to help me regarding the problem.
Compiling verilog file "../../u2_core/u2_core.v" in library work
Module <atr_controller> compiled
Compiling verilog file "../u2_rev3.v" in library work
Module <u2_core> compiled
Module <u2_rev3> compiled
No errors in compilation
Analysis of file <"u2_rev3.prj"> succeeded.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
ERROR:HDLCompilers:87 - "../../../eth/rtl/verilog/MAC_rx/MAC_rx_FF.v"
line 134 Could not find module/primitive 'fifo_xlnx_2Kx36_2clk'
ERROR:HDLCompilers:87 - "../../../eth/mac_txfifo_int.v" line 35 Could
not find module/primitive 'fifo_xlnx_512x36_2clk'
-->
Total memory usage is 131520 kilobytes
Number of errors : 2 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
Process "Synthesis" failed
INFO:TclTasksC:1850 - process run : Generate Programming File is done
I hope to hear a remedy for this problem,
Once again thanks in advance,
Mahesh
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