Tiago Rogério Mück wrote:
I tried the makefile in u2_rev3 but got some erros:
>>> Creating project: build/u2_rev3.ise
ERROR:HierarchicalDesignC:40 - Failed to close Project repository.
HDProject
data may not have been properly written to the Project file.
ERROR:HierarchicalDesignC:40 - Failed to close Project repository.
HDProject
data may not have been properly written to the Project file.
>>> Setting: Project[family] = Spartan3
ERROR:TclTasksC - ERROR:TclTasksC:project_041: Internal error. Error getting
SynthesisOnly default view.
>>> Setting: Project[device] = xc3s2000
>>> Setting: Project[package] = fg456
>>> Setting: Project[speed] = -5
>>> Setting: Project[top_level_module_type] = HDL
>>> Setting: Project[synthesis_tool] = XST (VHDL/Verilog)
>>> Setting: Project[simulator] = ISE Simulator (VHDL/Verilog)
ERROR:TclTasksC:project_095 - project set : Unknown property "simulator".
Type [project properties] for more information.
while executing
"project set $key $opt"
invoked from within
"if ![string compare $process "Project"] {
project set $key $opt
} else {
project set $key $opt -process $process
}"
invoked from within
"if $state {
set key $opt
set state 0
} else {
puts ">>> Setting: $process\[$key\] = $opt"
if ![string compare $process "Project"] {
..."
(procedure "set_props" line 7)
invoked from within
"set_props "Project" $env(PROJECT_PROPERTIES)"
invoked from within
"if [file isfile $env(PROJ_FILE)] {
puts ">>> Opening project: $env(PROJ_FILE)"
project open $env(PROJ_FILE)
} else {
puts ">>> Creating project: $..."
(file "../tcl/ise_helper.tcl" line 43)
make: *** [proj] Error 1
I've found some info about this erros on
http://www.xilinx.com/support/answers/29765.htm , but I wasn't able to
make it work. So I tried the hard way. I created a project and manualy
configured it acording to the makefile.
I'm not sure why this isn't working for you. Are all the xilinx
programs in your path?
There was also another error in the implementation step when I tried to
build the code:
ERROR:NgdBuild:789 -
"/export/tiago/TCC/implementacao/usrp2/fpga/top/u2_rev3/u2_rev3.ucf" Line
326: 'CLOCK_DEDICATED_ROUTE' is an invalid constraint name.
Commenting that constraint solves the problem and the project builds
fine. I uploaded the bitstream to the usrp2 and it seems to be OK.
Are these the errors related to the bugs in ISE 9.1 that you talked
about? Is there some consequence in removing the 'CLOCK_DEDICATED_ROUTE'
constraint?
Anyway, I'll try to get a more recent version of ISE.
Yes, that is one of the 9.1 errors.
Matt
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