Hi,
> On Sat, 3/28/09, slimchao <slim1...@hotmail.com> wrote:
>
> Hello,
>
> can anyone explain how implemented the CIC interploator
> Filter (how many
> stages) in the FPGA. if we want a interpolation of 32, the
> interpolation
> rate is 4 in the AD9860 (4x interpolation), sothat the
> interpolation is
> 32/4=8 in the FPGA (stages ??), am i right?
>
> thanks a lot!
>
> slimchao
See:
http://gnuradio.org/trac/wiki/UsrpFAQ/DDC
http://gnuradio.org/trac/wiki/UsrpFAQ/DUC
BR
Firas
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Hi Firas,
thanks! i am sure that a 4 Stage CIC Decimator is in the USRP FPGA DDC and
4x interpolation in the AD9860 (an interpolation rate of 4x is achieved
using both interpolation filters). but how many Stage CIC Interpolator is
in the FPGA at the TX path. i guess also 4 Stage CIC Interpolator in the
FPGA, am i right?? please correct me!
thanks again
slimchao
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