I've tested this here in my lab, using a signal generator for the SMA
reference input.

With firmware modified to automatically set the clock source to the
external reference, and to generate a test 10 MHz output waveform, I
get a good lock when the external reference is anywhere between -13dBm
and 10 dBm (142mV p-p to 2V p-p).

This is using revision 10467 for both the FPGA and the firmware.

Johnathan Corgan
Corgan Enterprises LLC


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