You are correct about the fft level not scaling with fft size. I remember putting this in some time ago, but it isn't there now, so I don't know what happened. In any case, I did some further analysis on the spurs. We are seeing 2 different things on the USRP1 and USRP2
The USRP1 definitely has a DC offset problem. I thought I had fixed this a long time ago, but I guess it never got put in there. It isn't hard to fix, but I'm busy with other things right now. I would be happy to accept a patch for the verilog code.
On the USRP2, I believe that what you are seeing is perfectly reasonable. If you put in a full scale signal (about +8dBm), the peak shows up at about 31dB (on the arbitrary scale on the display, assuming you use 8192 points in the FFT). You are seeing the 12.1 MHz (DC) spur at about -60 dB, which is about -90 dB Full Scale. Since we are only sending 16 bit numbers over the bus, you can't expect to have better dynamic range than about 96dB.
Matt ILKYOUNG KWOUN wrote:
Guys, I managed another comparison test last night. http://zoolu.co.kr/episodes/6 *. Test tone signal quality I used a siggen as good as I could get. :-) According to the spectrum analyzer, it seemed that the siggen did not generate any noticeable harmonics(1st and 2nd pictures). Actually, I raised the power level up to 0 dBm when I tested last night. But took the snapshots with -34dBm level. *. Signal level I reduced the signal level down to -34dBm just to avoid any possible input level saturation. I believe it is low enough. :-) My questions 1. Still get spurs As you can see in 3rd and 4th pictures, I still have quite significant spurs in band. However, when I match the local oscillator frequency with that of test signal like picture #5, all spurs were gone away. So, I am still suspicious if those spurs came out of the LO leakage from the FPGA CORDIC. (I don't believe that happens in the digital domain. Probably, the digital switching noise spilled over to the analog part and it was fed to ADC input. That's my best guess.) Is there any comments, corrections, or suggestions? I probably have to figure out Kyle Pearson's work on rounding in FPGA that Frank mentioned before. 2. Automatic signal level scaling I made comparison between different FFT sizes and the peak level varied. As you can see, The Peak level was -11dB with FFT size of 8192 and -19dB with 1024 while the absolute signal power level was -34dBm. The differences are about 8 dB and it explains because the FFT size scale is 8(=2^3) times. Which part of the code does the automatic scaling? Ilkyoung. _______________________________________________ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
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