Hi, I've recently started looking at the Spartan3 ISE projects.? I started trying to re-synthesize the ISE projects, while using the "u2_rev3.ucf" file, I realized that I had to enable the "Allow Unmatched LOC Constraints" option, which seems okay since some declared signals might be used.? However I also had to comment out the following signals from it
#NET "clk_to_mac" TNM_NET = "clk_to_mac"; #TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %; #NET "clk_fpga_p" TNM_NET = "clk_fpga_p"; #TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %; #NET "cpld_clk" TNM_NET = "cpld_clk"; #TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %; #NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK"; #TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %; #NET "ser_rx_clk" TNM_NET = "ser_rx_clk"; #TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; #NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE; I looked for the signals to see if they're used in any of the verilog files, I saw them instantiated but never used I'm also assuming that the "clk_fpga" signal is the main FPGA clock.? Since the signals I commented out are clocks, did I just do something wrong and the project supposed to synthesize without this modification.? Or are my change wrong? Thanks in advance, Al Fayez
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