Hi,
a week a goo I asked if someone could please explain how the Rx MUX is
to be set, unfortunately I have not had any luck with an answer. I have
read the USRP FAQ but I find the answer unclear, e.g. because I do not
know the mapping of ADC number to side. In addition it is also unclear,
to me, if the answer talks about a single bit position or a binary
number (here several bits):
>From the FAQ:
The MUX is like a router or a circuit switcher. It determines
which ADC (or constant zero) is connected to each DDC input. There are 4
DDCs. Each has two inputs. We can control the MUX using usrp.set_mux()
method in Python.
The Mux value is calculated by:
3 2 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1
0
+-------+-------+-------+-------+-------+-------+-------+-------+
| Q3 | I3 | Q2 | I2 | Q1 | I1 | Q0 | I0
|
+-------+-------+-------+-------+-------+-------+-------+-------+
Each 4-bit I field is either ADC 0,1,2,3 Each 4-bit Q field is
either ADC 0,1,2,3 or 0xf (input is const zero) All FPGA DDC Q's must be
0xf or none of them may be 0xf. We tell each input DDC input (I0, Q0, I1
... I3, Q3) which ADC is connected to it by using 4 bits (0, 1, 2, 3 or
0xf). So a 32-bit integer would be enough for all 8 inputs to know which
ADC is connected. Of course an integer in hexadecimal system will be
more convenient if we want to use the set_mux() method. For most real
sampling applications, the Q input of each DDC is constant zero. So
quite often we don't need to modify the standard configuration of the
FPGA. Actually it is anticipated that the majority of USRP users will
never need to use anything other than the standard FPGA configuration.
1: For example the I-data ADC is controlled by a 4-bit field: does that
mean 0=0001 1=0010 2=0100 3=1000, or does it mean 0=0000 1=0001 2=0010
3=0011?
2: Which ADC is connected to which side of the USRP is 0,1 on side A?
3: How do I assign ADCs to Rx vs Rx2?
4: Does the following text imply that all Q=0 as the standard setting?:
For most real sampling applications, the Q input of each DDC is constant
zero. "So quite often we don't need to modify the standard configuration
of the FPGA. Actually it is anticipated that the majority of USRP users
will never need to use anything other than the standard FPGA
configuration."
I kindly ask some more knowledgeable to answer my question
/Ulf
My original Question
I have been trying to understand how to make an application where I use
two USRPs one acting as TX and the other as RX. Both the USRP have two
RFX2400 daughter boards so I would like to transmit two streams and
receive two streams. My starting point was the
"fm_tx_2_daughterboards.py" which I think I understand.
First question (Tx):
-The tx_mux setting for the top_block in "fm_tx_2_daughterboards.py" is
0xBA98 which is understandable. If I use
MuxVal=usrp.determine_tx_mux_value(self.u,(1,0))+usrp.determine_tx_mux_v
alue(self.u,(0,0))
I get 0x9898 which I do not understand.
Then I wanted to write a corresponding rx_2 and I started with the mux
from the description of the rx mux, here I don't know which ADC is on
RxA and RxB so I cannot figure out the appropriate setting.
In case I use
MuxVal=usrp.determine_rx_mux_value(self.u,(0,0))+usrp.determine_rx_mux_v
alue(self.u,(1,0));
I get 0x24, which kind of odd ? If I do
usrp.determine_rx_mux_value(self.u,(0,1))
I get an error (I thought this meant side A Rx2)
I guess I'm all confused and don't understand the documentation, can
someone please explain the Rx mux and the automatic setting?
/Ulf
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