On Tue, Aug 26, 2008 at 07:38:47PM -0500, Ketan Mandke wrote:
> The timestamp for packets should corrsepond to the
> time when the first sample in the packet is actually "strobed" off the
> ADC. This would also insure that the two channels on the board would
> have synchronous timestamps (i.e. if a sample is strobed in from each
> channel at the same time, the packets formed from the proceeding
> samples should have the same timestamp).
Ketan,
We definitely want the two channels to have synchronous timestamps,
and we want the Tx and Rx to share a common idea of time. However
I think that the reference point for timing is at the edge the DSP
pipeline, not the ADC or DAC. (I thought it was at the ADC/DAC
originally too, but after a fair amount of reflection (and strong
prodding from Matt, I've come around to this point of view.))
The challenge is easy to see if you look at the Tx direction. The
pipeline and group delay through the Tx DSP pipeline varies depending
on many configuration options, including the interpolation rate, any
filters, etc. The host is capable of knowing and computing this
delay, and thus can achieve the goal of precise time of transmission,
even though the reference point is at the near edge of the DSP
pipeline, not the DAC. Same story on Rx.
This also implies that the host should preload enough zeros into the
head of the burst such that the signal of interest gets out of the DAC
at the desired time.
Does this make sense?
Tx timing Ref Pt
|
v
USB --> buffers ---> DSP pipeline --> DAC
USB <-- buffers <--- DSP pipeline <-- ADC
^
|
Rx timing Ref Pt
Eric
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