Matt Ettus wrote:

What are your PLL settings? If you minimize the R divide ratio, you can eliminate this. The larger R divide will put you further from right on frequency, but the DDC will put you right back in the right place.

Yes.  You can also try setting the frequency to 1575 rather than 1575.42;
this results in more favorable PLL settings by default, and then one can
remove the frequency offset at baseband as a separate frequency translation
step.

How sudden are the shifts and how often do they happen?  Do they look
like frequency spikes (phase steps) or frequency steps (phase ramps)?
If the dbsrx PLL were to slip occasionally, I guess one would expect
the former, not the latter.  Could try feeding the dbsrx with a nice
strong tone from a signal generator to get a better view of its phase
purity once it's been through the entire USRP chain.

Some TCXOs suffer from sudden jumps over temperature, but this
doesn't match your experience, since the TCXO is on the motherboard
and would affect both dbsrx's equally.

Cheers,
Peter Monta



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