Thanks for your reply!
I'll try it ASAP.
:)
--- Eric Blossom <[EMAIL PROTECTED]> wrote:
> On Mon, Mar 31, 2008 at 05:00:17AM -0700, James
> Worthington wrote:
> >
> >
> > I have a problem. I newly purchased a Basic Rx
> > daughterboard and I tried using the usrp_oscope.py
> > file to test whether or not my daughterboard
> works.
> >
> > Unfortunately, only the Rx-A portion seems to be
> > working. Is this always the case? Is there
> something
> > that I should do so that I could receive from the
> Rx-B
> > portion.
>
> $ foo.py -R a:1
>
> > I mean, it's really weird that I have two
> > input ports (since there are two SMA connectors
> that
> > serve as input to the Basic Rx Daughterboard), but
> I
> > can only pass input to one of them.
> >
> > Is the RX-B just a decoration? Could I use both
> ports
> > simultaneously?
>
> Yes.
>
> Try
>
> $ usrp_oscope.py --help
>
> Eric
I use both RX-1 and RX-2 and a single Basic RX daughterboard.
ADC1 and DDC1 are used for RX-A, and ADC2 and DDC2 for RX-B.
Followings are a part of my script.
######
class wfm_rx_block (gr.top_block):
def __init__(self,f_time,f_data):
gr.top_block.__init__(self)
self.state = "FREQ"
self.freq = 0
### frequencies ###
freq1=10000000. # 10 MHz, just for example
freq2=12000000. # 12 MHz
### filter setup ###
adc_rate = self.u.adc_rate()
usrp_decim = 200
self.u.set_decim_rate(usrp_decim)
usrp_rate = adc_rate / usrp_decim # 320 kS/s
chanfilt_decim = 1
demod_rate = usrp_rate / chanfilt_decim
audio_decimation = 16
audio_rate = demod_rate / audio_decimation # 20 kHz
chan_filt_coeffs = optfir.low_pass (1, # gain
usrp_rate, # sampling rate
15e3, # passband cutoff
25e3, # stopband cutoff
0.1, # passband ripple
60) # stopband attenuation
audio_sink = audio.sink(int(audio_rate),
options.audio_output,
False) # ok_to_block
#USRP with 2 channels
self.u = usrp.source_c(0,nchan=2)
# RX-1 to DDC1, RX-2 to DDC2
self.u.set_mux(0xf0f0f1f0)
# select RX-A daughterboard
self.subdev = self.u.db[0]
# deinterleave two channels from FPGA
di = gr.deinterleave(gr.sizeof_gr_complex)
# wire up the head of the chain
self.connect(self.u, di)
# DDC-1
ok, baseband_freq0 = self.subdev[0].set_freq(freq1)
# DDC-2
ok, baseband_freq1 = self.subdev[1].set_freq(freq2)
# DDC-1
r0 = usrp.tune(self.u, 0, self.subdev[0],freq1)
# DDC-2
r1 = usrp.tune(self.u, 1, self.subdev[1],freq2)
chan_filt = gr.fir_filter_ccf (chanfilt_decim, chan_filt_coeffs)
self.guts = blks2.am_demod_cf (demod_rate, audio_decimation,
15e3,25e3)
self.connect((di,0),chan_filt)
self.connect(chan_filt,self.guts,(audio_sink,0))
chan_filt = gr.fir_filter_ccf (chanfilt_decim, chan_filt_coeffs)
self.guts = blks2.am_demod_cf (demod_rate, audio_decimation,
15e3,25e3)
self.connect((di,1),chan_filt)
self.connect(chan_filt,self.guts,(audio_sink,1))
######
Susumu Saito
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