Hi, I had a look around the SVN repo when the most recent USRP announcement was made and I noticed that the .ise project file has been committed.
In my experience this doesn't work very well - project navigator touches it everytime you do just about everything. Also I've had PN crash when you open an ise file from another platform. It also has a tendency to corrupt it and recreating it by hand sucks. To work around this I have a script that uses the 'pjcli' tool, it looks like this.. # Create the project NewProject(foo.ise) # Set basic properties SetProperty(Device Family, spartan3) SetProperty(Device, xc3s400) SetProperty(Package, tq144) SetProperty(Speed Grade, -4) SetProperty(Top-Level Module Type, HDL) # Add the sources AddSource(foo.v, Verilog Design File) AddSource(foo.ucf, foo) AddSource(alu.xco, Coregen Design File) AddSource(alu_wrap.v, Verilog Design File) # Test bench sources AddSource(foo_test.v, Verilog Design File) SetProperty(Simulation Run Time, 5000 ns, foo_test_v, Simulate Post-Place & Route Model, 9, foo) # Close the project to tidy up CloseProject() To use it you run.. pjcli -f foo.npl -- Daniel O'Connor software and network engineer for Genesis Software - http://www.gsoft.com.au "The nice thing about standards is that there are so many of them to choose from." -- Andrew Tanenbaum GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8C
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