Brian- > > 2) Does your new FPGA code require the next-gen USRP, with Spartan 3 FPGA? > > My understanding is that capacity is very > > limited in the Cyclone, which is an old FPGA (around yr 2002 time-frame). > > If you have a single, specific application in mind, you should be able > to reduce down the size taken in the USRP FPGA significantly. > > The original USRP FPGA was designed to be able to handle the most > minimal decimation (4 by the CIC and 2 by the halfband FIR filter, I > believe) which has the FIR computing every 8 clock cycles and an > effective bandwidth of 8MHz. > > It was also designed for the CIC to handle large decimation rates > which increases the "bit growth" of that filter. If you specifically > have a bandwidth and decimation rate you're interested in (or even a > small range of decimation rates) then you should be able to change the > CIC filter to use significantly less space. Moreover, if you're > decimating more than 4 at the CIC, you can use more clock cycles and > less instantiated soft multipliers for the FIR filter in the FPGA.
I think the biggest concerns with Cyclone I are lack of multipliers and low amount of internal mem (26 kbyte for the EPC1C12). > Just curious, what are you specifically looking to do? Do you need > the ranges for the CIC decimation, or just a few select values? Can > you handle having less CIC decimation and more FIR decimation? What > waveforms are you looking at which causes latency to be so tight? 802.11b (more specifically VoIP-over-WiFi), GSM (EDGE), and eventually 3G (HSDPA) waveforms. I've seen discussions and specific deadline figures for 802.11b, but not yet for the others -- do you know any web pages that show comparisons? Thanks. -Jeff _______________________________________________ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
