Eric Blossom wrote: > For now, don't worry about getting it into dB on the FPGA. > The representation can be manipulated on the host. > OK, so how do I get post-ADC rssi out of the USRP for any arbitrary daughtercard?
My radio astronomy receiver could benefit from this, especially if the RSSI is low-pass filtered to some degree onboard the FPGA. Part of my host side stuff computes RSSI from the samples coming from the USRP (by squaring and low-pass filtering). I could probably save about 20% of my CPU load if I could get that squaring, and at least a first-stage low-pass filter done on the FPGA.
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