Is it possible (in a relatively easy manner) to make the data from the ADC (or, probably better and more doable, from the DDC) available at the external pins of the USRP and to get external data from the USRP pins and feed that to the PC? Essentially we want to use the FPGA board as a front-end preprocessor.
Here is what we are trying to do: Instead of passing the data up to the PC and processing it there, we would like to take the data (the 12-bits of I data should be sufficient for our needs) and pass it off to an external FPGA/DSP board. After that board is finished cranking on it, we would like to pass the data back to the USRP for upload to the PC over the USB cable for further processing. We don't need to feed the raw IQ data to the PC at all. We realize that this sort of defeats the purpose of SDR but, for what we are doing, we have a lot of front-end processing that has to be done and we need to show that it can be done efficiently in parallelized hardware. It would be nice if it can be done without having to delve into the USRP FPGA firmware code. We are willing to accept a significant performance penalty and run at very low data rates because this is purely proof-of-concept type stuff. In other words, if we have to read the IQ data from USRP normally and then send the I data back down to the external pins and then read another set of pins to get processed data back we are willing to do that as a start. Thanks. _______________________________________________ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
