Eric Blossom wrote:
Not very hard.
Awesome.
There is a loopback interface in the current FPGA code. It's enabled
by writing to the FR_MODE register. Grep the verilog for "loopback",
and look at fpga_regs_common.{h,v}
Thanks :D
We want to test out using the loopback eventually, and overall I'm
wondering how much time from when I finish the test code to putting a
packet on the interface so I can plan out this week. :)
I don't know. When will you have the rest of the host code written?
Ahh that wasn't a question, it was me explaining my question. More like "when i
finish the host code, since you know the interface to the USRP better than me,
how long would it take me to interface to it?" Was asking so I can gauge how
much time from when i finish the host code to actually putting them on the USRP
so I can warn Thibaud to be ready.
I suggest that you treat this like it's "your project", not "Eric's
project". I'm available to answer questions, respond to requests,
etc., but don't assume that the cavalry is coming ;)
Of course, I think you just misunderstood my wording :D
What's your next step?
Writing up some test code for my host code, starting on that now.
I'm working on mblock timeouts ;)
sweet
- George
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