On Fri, Mar 23, 2007 at 03:21:03PM -0700, Eric Blossom wrote: > On Fri, Mar 23, 2007 at 02:45:54PM -0400, Thibaud Hottelier wrote: > > > For each channel fifo, a process would wait for the timestamps to match > > the time register and then write the next <#samples> to the > > corresponding channel transmit chain at every tx_clock tick. > > Actually, the timestamp specifies the time that the sample is supposed > to hit the DACs, not the time that it enters the signal processing pipe. > This may take some thought to implement correctly, since the latency > through the pipe varies depending on the details of the pipeline and > the interpolation factor.
We may be able to finesse this by having some readable registers in the FPGA that allow the host to compute the appropriate offset to apply the the application supplied timestamps. Eric _______________________________________________ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
