Gregory W Heckler wrote:
To all concerned parties:
I think I've discovered the problem. My "tune" routine chose the R and
N dividers to minimize the difference between the command and desired
LO frequencies. For L1 this ended up being 64 and 25197. The refclk
was set at 4 MHz, producing an R divider frequency of 62500 Hz. For a
sanity check I enabled the debug output of the Max2118 chip, in order
to probe the comparison frequency on the CNTOUT pin. Probing the pin
produced a nice square wave at 31250 Hz. The inconsistency bothered
me, and I double checked my driver was writing the correct values to
the Max2118 registers, it checked out as ok. On a lark I decided to
sacrifice the LO error for a greater comparator frequency. After
changing the R value to 8 and N to 3150 I recorded some new data and
crunched it with my software receiver. To my amazement the phase
jitter went away. So, two questions:
One other observation --
If you properly tune the loop filter in both cases, there should be an
18dB phase noise difference (div by 8 better than div by 64) inside the
loop bandwidth for the 2 cases you list. Since we aren't changing the
loop filters (they are passive components on the board), it can be even
worse. The components on the board are optimized for a 1 MHz compare
frequency.
These 2 factors can easily account for the performance differences you
are seeing, and going to a div-by-4 would probably improve it more.
There is very little cost to using a very coarse frequency step in the
PLL since we have very fine tuning capability ( ~ 14 millihertz) in the
digital downconverter. Thus, tuning the LO exactly on-frequency is of
no benefit, and actually makes things worse. This is why we use 4 or 8
MHz steps in the RFX-series boards.
Matt
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