On 3/5/07, Brian Padalino <[EMAIL PROTECTED]> wrote:
On 3/5/07, [EMAIL PROTECTED] <[EMAIL PROTECTED]> wrote: > (Found the Reply to All button!)
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That Analog Devices AD9235-65 looks like it's good if you want to sample at something like the USRP is doing right now - 64MHz. So what you'd be looking at is an oscope with a 500MHz bandwidth and a 64MSPS sampling rate. You could possibly double that if you did some cascading of the ADCs and used the opposite edge of the clock to also clock into a different ADC - giving you (effectively) double the samples per second. Which brings me to another important feature which is the clocking. To get a good representation of your incoming signal, you should have a pretty good reference clock with a VCXO or VCTCXO - especially if you want to do that high IF sampling. Those signals are moving so quick, you really need a super stable reference to nab them at the right time, otherwise your aliased image has a bit more noise.
Yeah, that indeed is an important issue that needs a very detailed and thought-out solution. One thing I'd like to be able to do some day is have maybe three of these devices all 100 meters from my computer arranged in a triangle and then triangulate signals using the Time of Arrival principle. I might be able to eventually construct an antenna array that isn't just directional, but also aware of distance. 65Msps wouldn't be enough for useful resolution, but it's a start. :) I would have to co-ordinate the receivers exactly to do this... Could it be possible to supply a stable clock over Ethernet? Couple it to the -48VDC? =)
If all you want to do is take the ADC data and shove it off to the PC to process, you need a really small FPGA that has just a few block rams in it to store for FIFOs. If you wanted to do more signal processing within the FPGA, you should look more towards a mid-sized low-end FPGA (Spartan 3E, Cyclone II, Lattice Semi) with embedded multipliers. An XC3S500E should run you around $20 and have a good amount of resources in there to run your gigE interface state machine and do some filtering - possibly an FFT or two as well. Learning Verilog should take a back seat to understanding your receive chain and how you want to process your incoming signals. Are you going to try to really process everything on the host side of things, or would you like different FPGA loads to be able to reduce down that massive data exchange and process less on your host? Parts are available for all different prices - but be sure to solve your problem and not just put together something that has a kitchen sink. You had wanted an oscope / spectrum analyzer / SDR. Is 500MHz bandwidth good enough for you? Do you want more? Is 64MSPS the digitizing rate you want to hit? What range and resolution bandwidths do you want for your spectrum analyzer? 0-10MHz at 1kHz RBW? Listing out your requirements / wish list might be a good idea before just saying you want to build this generic cheap SDR board.
I think that, realistically, I will have to do something with the data already at the FPGA. Be it pre-processing or decimation I do not know yet, nor can I guesstimate due to lack of experience. PA3FWM in the link Henry posted managed to deal with 2.5Msps, but I don't know his bit rate. I've decided in the past that I would be happy with being able to see just 1MHz of bandwidth at the time, and PA3FWM seems to have exceeded that. The benefit of using a high-speed ADC in this case would not be voided, since we could still do a lot of mojo that one can't do with a radio that requires a tuner. The lack of tuner in itself makes the device cheaper too... And what's "RBW"? =) -- Nos _______________________________________________ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
