Hi Lance, On 12/14/06, seph 004 <[EMAIL PROTECTED]> wrote:
Hi It seems the more I read through the fpga code, the more confused I get. There are a few things I'm unsure about: In the fpga DDC, are I and Q samples being generated from complex samples? The adc_interface module just seems to multiplex the same complex sample on to 2 lines. It would seem then that if the CORDIC module can muliply the sample with a sine and cosine at the carrier frequency, then I and Q samples should be produced. However, many diagrams around label the lines as I and Q before this stage, and it would seem then that I Q down conversion is done in analogue on certain daughterboards. Are I and Q channels generated in the daughterboards or in the DDC?
The ADC interface module takes care of demuxing the received signal into I and Q signals. Then every pair of IQ is routed to a DDC.
From looking at the debug pin code, and the code for synchronizing two USRP's, is it possible to receive a complex signal from a daughtboard and also use it to listen for an external digital trigger signal that can be used within the FPGA?
Also, from a response to another person's query, I noticed that Eric
mentioned that the basic daughtboards could not transmit or receive any signal lower than 100 kHz. Is there no way to receive a signal around 40 kHz? Perhaps with another daughtboard?
Try LFRX. Also, you can take a look at the following document http://acert.ir.bbn.com/viewvc/gr-ucla/trunk/doc/usrp.pdf?revision=HEAD it has an explanation of the different building blocks implemented in the FPGA Regards
Lance
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