On Thu, Nov 16, 2006 at 01:11:15AM -0800, seph 004 wrote: > Hi > > I'm still trying to figure out the problem in my code. I think that > along the way I misunderstood the purpose of the write_count > register. How does it actually work? WR triggers every time a 16 bit > packet is ready from the FX2 doesn't it?
write_count counts from 0 to 256, then back to 0. It's at 256 when WR is still asserted but there's really no data to receive. This works around some strange behavior in the FX2 GPIF interface and/or programming. > The wreq trigger of the FIFO is triggered by (WR & > ~write_count[8]). Does this mean that only 256 16 bit samples enter > the FIFO before the WR is removed? Why is this? How could I > determine exactly when there is an I or Q sample that must be > written into the FIFO? .wrreq tells the FIFO when data should be written to the fifo. So, we write when (WR & ~write_count[8]). That is, when WR is asserted, but the count does not have 0x100 bit set. As I recall, WR is asserted an extra cycle, and the counter trick works around this. You may want to take a look at the Altera Cyclone documentation. The block called tx_fifo is one of their standard blocks. It's the dual clock version of the fifo, and is used (amongst other things), to bridge between the USB clock domain (.wrclk(usbclk)) and the signal processing clock (.rdclk(txclk)). Eric _______________________________________________ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
