Hi,
in the receive path, the decimation is handled by the rx_chain.v module. That module also takes care of the digital down conversion to baseband using the CORDIC algorithm.
Oussama.
On 11/9/06, Lin Ji <[EMAIL PROTECTED]> wrote:
Hi,For my work I need to do some time stamping on some signal samples. For this purpose I need to modify a little the FPGA on the USRP. I suppose .\usrp-0.12\fpga is the right place to look at. There's a bunch of HDL design files in the folder, I wonder which of them have been used to handle the signal sampling and decimation? All I need to do is to add some additional clock information onto the samples.Thanks/Lin
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