I am looking at the transmission buffer (tx_buffer.v) verilog code. So it seems that it uses two clock signals. the txclk signal is used to read from the fifo_4k while the usbclk signal is used to write to the fifo_4k.
What are the clock speeds for those clock signals?
I believe I read in a previous email to the mailing list that the master_clock runs at 64MHz. Is that correct? Also, it appears to me that the master clock does not come form the GPIF bus of the USB controller. Where does that signal come from? Is it just an on board clock?
What is the speed of the usb clk?
Thank you ahead of time for any clarification on the matter.
Oussama.
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