On Dec 19, 2005, at 3:48 PM, David wrote:
I am currently trying to implement a coherent receiver with the same
results that it sounds like Blue Sky has gotten. We have tried many
things to compensate for the offset, but there still seems to be shift
form 20Hz to 3kHz depending on the channel desired.
I have tried your suggested set_freq method found in the
usrp_nbfm_rcv.py file, but to no avail. Perhaps I have misunderstood
your advice.
Currently I input a sinusoid (22MHz) from a signal generator directly
to the basic Rx board. I down convert the signal to an intermediate
frequency of 1MHz (sampling at 4MS/s across the USB) and then using
the xlating filter as a low pass filter (decimating to 250kS/s), I
attempt to downconvert the signal with the offset calculated using the
usrp.tune function.
unfortunately when I attempt to use 22MHz as my center frequency, the
usrp.tune function doesn' t see any error...when I use a less rounded
number (22.0003MHz), I get a calculated offset, but I am still left
300Hz or so from baseband.
into the usrp.tune function I have used (self.u, self.subdev, 21MHz)
where 21MHz is the frequency setting of the NCO desired in the
USRP...is this the wrong value to use here?
Is there anyway that this DDC resolution could be modified...perhaps
within the FPGA code?? Any suggestions would be appreciated. Thanks.
david scaperoth
On Wed, Dec 07, 2005 at 02:51:58AM -0500, Blue Sky wrote:
> I am trying to build a AM receiver by using USRP. I did setup the IF
> frequency to 1.43 MHz by using set_rx_freq. I was sending a 1 Khz
signal 90%
> modulated at 1.43 MHz carrier. I should get something from the USRP
output
> just the 1 KHz sine wave. But for some strange reason I am not
getting that.
> I am getting some extra 333 Hz freq signal with it. I dont' know
where is
> the problem. So, I am guessing the NCO-CORDIC is not completely
removing my
> carrier frequency. I saw the waveform just after the USRP it's the
same with
> some extra frequency. Anybody's help and thought would be highly
> appreciated. Thanks.
The FPGA DDC has a finite frequency step. If you're worried about the
333 Hz, you'll need to follow it up with a software DDC
(gr.freq_xlating_fir_filter_xxx: s/w DDC plus channel selection
filter).
Take a look at gnuradio-examples/python/usrp/usrp_nbfm_rcv.py
Skip all the GUI cruft, and look at the set_freq method.
It uses the high level daughterboard independent method to control the
(possibly null) analog front end and the FPGA DDC, then follows it up
with
a software DDC to handle any residual frequency offset.
Eric
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