On Thu, Oct 20, 2005 at 12:01:32PM -0700, Eric Blossom wrote:
> On Thu, Oct 20, 2005 at 12:03:31PM -0600, David R. Palchak wrote:
>
> If you only need two independent Tx channels, the quick fix is to use
> two Basic Tx daugherboards. This is supported. Just tell the USRP
> that you're using two channels of data, then provide a stream with two
> interleaved channels of I & Q data. If you like, I can whip up an
> example. Let me know.
>
> Eric
Additional thoughts:
If you don't need digital up-conversion, I don't think it would take
much to get two independent channels out. You should be able to use
the existing FPGA and host code, and just manually jam the right magic
values into the AD9862 registers 19 and 20. Make sure that you
continue to run the 4x interpolator on the AD9862 so all the data
rates remain the same.
You can write the AD9862 regs from python using:
u = usrp.sink_s(...)
u._write_9862(which_codec, regno, value) # note the leading _
# which_codec is 0 or 1 for side A
or B
Look in usrp_standard.cc at usrp_standard_tx::usrp_standard_tx to see
how we normally setup these registers.
Eric
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