On Wednesday 20 July 2005 14:23, Eric Blossom wrote:
> Matt & I are sorting out a problem with some new fpga code right now.
> I'll get them in a bit later today.

For the sake of those following CVS, when should it be safe again to build a 
bitstream from the CVS verilog?  Or do you need testers for some of this?  
How dangerous to USRP hardware could tracking fpga CVS be?  I see several 
changes in the current CVS, and it looks interesting.

You must have read the Web fad article, seeing the All Your Frequency Are 
Belong to Us code example.  :-)
-- 
Lamar Owen
Director of Information Technology
Pisgah Astronomical Research Institute
1 PARI Drive
Rosman, NC  28772
(828)862-5554
www.pari.edu


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