Guys, I remember someone gave me an answer to a similar question in the past regarding the Digital upconverter in the TX path that is implemented inside the ADC chip.
I have a similar question for the DDC in the RX path which is implemented in the FPGA: On the receiver path, the DDCs perform complex or real multiplication? My guess is the latter, ie, if the input signal (from the MUX) is si(t) in the I input of the DDC and sq(t) in the Q input of the DDC, and if the CORDIC frequency is fc, then the output complex signal is [si(t)+j sq(t)] exp(j 2 pi fc + phi) Is this right? Thanks Achilleas _______________________________________________ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
