On Monday 02 May 2005 00:16, Tim Ansell wrote: > The question is how would you get this into a computer? If we round it > up to 16 bits, it makes 4.6 Gigabytes per second. Would a FPGA even be > able to keep up? Could people a lot smarter then me, discuss how this > chip could even possibly be used?
You would have to widen the data path to reduce clock rates. Something like an SRC MAP processor can handle 4.8GBps rates on GPIO, but the GPIO is 216 bits wide. So, you'd build a shift register of sorts, clocking in x 16 bit samples across the width of the register and then dumping all the bits in one swoop. Say you did 160 bits; you'd then be able to clock in at 460MWps (where a word is 160 bits). That would be a ten-stage register pipeline with serial words in, parallel words out. The SRC MAP processor is very expensive, by the way, and interfaces with the host CPU using their SNAP system, where the dat comes in on a DDR-SDRAM interface, the only thing in a PC that can hope to keep up with those rates. Of course, the MAP processor itself is a trio of high-speed Xilinx FPGAs, and SRC provides tools to program the FPGA's from C or Fortran; they call it reconfigurable computing (it was featured a few months back in LJ). So the FPGA's on the MAP do you decimation and DDC prior to hitting the CPU. We have a grant application for an SRC MAPstation with 16 200Msps 8 bit ADC's; cost is going to be around $160K. We're getting our feet wet in FPGA stuff with the USRP in the mean time. -- Lamar Owen Director of Information Technology Pisgah Astronomical Research Institute 1 PARI Drive Rosman, NC 28772 (828)862-5554 www.pari.edu _______________________________________________ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
