Dear all,
I read in the USRP description that the Receiver path has 4 ADC's and in the FPGA there are 4 DDC's implemented. Each DDC has 2 inputs (I and Q) and two real (or one complex) output. The MUX is swithcing the output of the 4 ADC's (or the value zero) to the 8=4x2 inputs of the DDC's.
I attach three eps files with what I understand is the block diagram
of this implementation. It is assumed that the standard Rx dboard is on side 0 and the tv_rx board is on side 1.
Here are some questions:
Are the connections from the daughterboards to the ADC's hardwired in the USRP the way it is shown in the figure, ie, RX-A to ADC-0, RX-B to ADC-1 and the IF output of the TV-RX to both ADC-2 and ADC-3 ?
Why is there a need for 4 DDC implemented in the FPGA?
How exactly are the 4 complex streams multiplexed into the USB port? are we always sampling one from each of the four, or can we control it so that we always select say DDC-0 ? How is this controled in software?
According to usrp_wfm_gui.py the correct MUX seting for listening to
FM is 0x f0 f0 f0 f2.
These connections are shown on the second eps file.
It seems to me that this is not the way the tv_rx output should be connected to the DDC's. To start with, why are we zeroing all Q channels? If this is done then we should be getting always a complex number with zero imaginary part...
It seems to me that the correct setup is 0x 32 32 32 32,
as it is shown in the third figure.
(however, I do have a very nice FM reception even with the f0f0f0f2,
so I guess I am missing something)
Thanks, Achilleas
usrp1.eps
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