On April 6, I posted: > It looks like my code is in there, attempting > to read the JTAG ID chain, and getting all 1's. Not > the right answer, of course, but I'm on my way.
I don't promise that anyone outside my project cares, but I now have a good start making an Avnet V4LX evaluation board http://www.em.avnet.com/evk/home/0,1719,RID%253D0%2526CID%253D16863%2526CCD%253DUSA%2526SID%253D4742%2526DID%253DDF2%2526SRT%253D1%2526LID%253D18806%2526PVW%253D%2526BID%253DDF2%2526CTP%253DEVK,00.html sing with the USRP firmware. I use the JTAG hooks from the CY7C68013 to read JTAG IDs, and program the Xilinx Virtex-4 FPGA: 977488 bytes in 7.66 seconds. My JTAG routines are pin-compatible with the original USRP fpga_load_begin(), fpga_load_xfer(), and fpga_load_end(). I can provide my code on request. On to explore the data transfer capabilities of this setup: I guess that will count as "dancing". - Larry
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